Embedded/Firmware Engineer

About the Role

We build measurement systems where timing is the product. Our algorithms assume streams are sampled deterministically, timestamped consistently, and accompanied by enough diagnostics to know when reality violated the assumptions.

The Embedded/Firmware Engineer owns the on-device foundations: clock/timebase behavior, sensor I/O, deterministic acquisition, and “truth telemetry” that makes downstream co-timing and cancellation reliable.

This role is for someone who likes turning “should be synchronized” into provable timing behavior.

What You’ll Do

• Timebase control + characterization: configure and measure oscillator behavior, clock trees, PLLs/timestamp counters; quantify drift/jitter and expose it as telemetry.
• Deterministic sampling: design acquisition loops that guarantee sample timing (DMA, interrupts, double buffering); prevent dropouts and hidden resampling artifacts.
• Sensor I/O + synchronization: integrate sensors (ADC/I2S/SPI/I2C/UART/CAN/ETH as needed), align sampling across channels, manage latency budgets, and document timing paths.
• Timestamping & metadata: produce robust timestamp formats and metadata (device ID, firmware version, calibration constants, sample-rate truth, buffer health).
• On-device diagnostics: implement self-tests and health metrics (clipping/saturation, noise floor estimation, overruns, clock slip detection, temperature/voltage monitors).
• Calibration hooks: support gain/phase/offset calibration and persistence; make calibration state auditable and versioned.
• Data transport: reliably stream or log data (USB/UART/Ethernet/Wi-Fi/SD) with integrity checks and backpressure handling.
• Bring-up + validation: write bench tests and tooling to validate timing determinism end-to-end (scope/logic analyzer procedures, loopback tests, synthetic injection).

Concrete Deliverables

• A deterministic acquisition firmware that meets defined jitter/drift/dropout budgets.
• A timestamp + metadata contract consumed by the processing pipeline (stable across releases).
• An on-device diagnostics panel (serial/status frames or web UI) showing timebase, sampling, and sensor health in real time.
• A hardware/firmware acceptance test suite: clock drift characterization, channel alignment verification, dropout detection, regression tests for timing behavior.

Required Qualifications

• Strong embedded fundamentals in C/C++ (or Rust): interrupts, DMA, RTOS/bare-metal design, memory/performance constraints.
• Experience with timing-sensitive systems: sampling reality, clocking, jitter/drift, latency, buffering.
• Comfort with common interfaces (SPI/I2C/I2S/ADC/UART, etc.) and practical signal integrity concerns.
• Ability to build diagnostics-first firmware (health metrics, logs, reproducible bug reports).

Preferred Qualifications

• Experience with precision timing/sync: PTP/IEEE-1588, GPSDO discipline, PPS, NTP pitfalls, multi-device sync.
• Familiarity with DSP-adjacent embedded work (audio pipelines, RF front ends, multi-channel ADCs).
• Experience designing firmware for scientific workflows: calibration state, provenance, deterministic replay.
• Comfort collaborating on hardware bring-up (schematic literacy, debugging with scope/LA).

How You’ll Be Measured (First 60–90 Days)

• You ship a stable acquisition loop with known and measured timing properties (jitter/drift/dropout quantified).
• The device emits diagnostics that allow the algorithm team to detect timing violations automatically.
• The data pipeline can reproduce a run with a receipt that includes firmware build, calibration state, and sampling truth.
• You reduce “mystery failures” by making firmware behavior observable and testable.

Working Style

• You don’t trust clocks until you’ve measured them.
• You design for failure: if timing slips, it gets detected, logged, and surfaced—not silently absorbed.
• You like clean interfaces: stable metadata, explicit budgets, acceptance tests that settle debates.

Title & Level

Embedded/Firmware Engineer (mid-to-senior; can scale to Staff depending on ownership), partnering tightly with systems and algorithm teams.